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ADD EAX, 242424h 63 31 15 7 0 63 31 15 7 0 The upper 32 bits are cleared when Performing a Dword operation.Download PDF x86 Instruction Set ArchitectureBy Tom Shanley.

The operand sizes must match on most x86 instructions

ADD R9W, EAX You cannot perform a byte operation using a high register (AH, BH, CH, DH) and one of the new registers (R8B – R15B).

General-Purpose Registers (GPRs) R8D (“D” means a Doubleword access) Dword = 4 bytes R8W (“W” means a Word access) Word = 2 bytes R8W (“B” means a Bord access) Quadword = Qword = 8 bytes

General-Purpose Registers (GPRs) (Accumulator) (Base) (Counter) (Data)

Instruction Composition Average instruction size: 32-bit code: 3.4 bytes 64-bit code: 3.8 bytes

IRET / 1 / 0 IP DEC CX CX = 2 LOOP Lable1 JNZ Label 1.

Here is a small subset of the x86 instructions related to program flow:.

DX : AX SIMD operations (Single Instruction Multiple Data) Upper 16 bits Lower 16 bits.

SQRTPS MMX instructions x87 instructions.

A small sampling of the general-purpose and floating-point x86 instructions are shown below:.

MOV, Note: intel syntax (destination, source).

MOV, SI √ MOVS, moves data from one memory location to another.

MOV, BX move register data to memory.

MOV BX, AX move ax register to bx register.

MOV SI, 7000h move immediate to register.

Here are a few variants of the MOV and ADD instructions as examples:

A number of the x86 instructions have multiple variants.

ADD CX, AX (AX+CX => CX) Note: intel syntax (destination, source).

x86 is a CISC architecture with hundreds of instructions defined.

Jon Erickson, Hacking: the art of exploitation, No Starch Press, 2008.

Tom Shanley, X86 Instruction Set Architecture: Comprehensive 32- and 64- Bit Coverage, MindShare Press, 2009.